System Verilog Questions

1. What is the difference between a reg, wire and logic in SystemVerilog?
2. What is the difference between a bit and logic data type?
3. What is the difference between logic[7:0] and byte variable in
SystemVerilog?
4. Which of the array types: dynamic array or associative array, are good to model really large arrays, say: a huge memory array of 32KB?
5. Suppose a dynamic array of integers ( myvalues ) is initialized to values as shown below. Write a code to find all elements greater than 3 in the array using array locator method “ find ”?
6. What is the difference between a struct and union in SystemVerilog?
7. What is the concept of a “ref” and “const ref” argument in SystemVerilog function or task?
8. What would be the direction of arguments in any function in any system verilog function?
9. What is the difference between a packed array and an unpacked array?
10. What is the difference between a packed and unpacked struct?
11. Which of the following statement is true?
12. Given a dynamic array of size 50, how can the array be re-sized to hold 200 elements while the lower 100 elements are preserved as original?
13. What is the difference between “forever” and “for” in SystemVerilog ?
14. What is the difference between “case”, “casex” and “casez” in
SystemVerilog?
15. Which of the logical equality operators “==” or “===” are used in case
expression conditions for case, casex, and casez?
16. What is the difference between $display, $write, $monitor and $strobe in SystemVerilog?
17. What is wrong with following SystemVerilog code?
18. What is the difference between new() and new[] in SystemVerilog?
19. What is the concept of forward declaration of a class in SystemVerilog?
20. What is the difference between private, public and protected data
members of a SystemVerilog class?
21. Are SystemVerilog class members public or private by default ?
22. What is a nested class and when would you use a nested class?
23. What are interfaces in SystemVerilog?
24. What is a modport construct in an interface?
25. Are interfaces synthesizable?
26. What is a clocking block and what are the benefits of using clocking
blocks inside an interface?
27. What is the difference between following two ways of specifying skews
in a clocking block?
28. What are the main regions inside a SystemVerilog simulation time step?
29. What is a unique constraint in SystemVerilog?
30. How can we disable or enable constraints selectively in a class?
31. Given a Packet class with following constraints, how can we generate a
packet object with address value greater than 200?
32. What are pre_randomize() and post_randomize() functions?
33. Write constraints to generate elements of a dynamic array (abc as
shown in code below) such that each element of the array is less than 10
and the array size is less than 10.

34. What is the difference between “fork – join”, “fork – join_any” and
“fork – join_none”?
35. What is the use of “ wait fork” and “ disable fork” constructs?
36. What is the difference between hard and soft constraints?

37. Which keyword in SystemVerilog is used to define Abstract classes?
38. What is the difference between a virtual function and a pure virtual
function in SystemVerilog?
39. What does keyword “extends” represent in SystemVerilog?
40. What are Semaphores? When are they used?
41. What are Mailboxes? What are the uses of a Mailbox?
42 What is difference between bounded and unbounded mailboxes? How
can we create unbounded mailboxes?
43 What is an “event” in SystemVerilog? How do we trigger an “event” in
SystemVerilog?
44. How can we merge two events in SystemVerilog?
45. What is std::randomize() method in SystemVerilog and where is it
useful?
46. Is it possible to override a constraint defined in the base class in a
derived class and if so how?
47. Identify what could be wrong if following function is called in
SystemVerilog constraint as below?
48. What is a virtual interface and where is it used?
49. What is the concept of factory and factory pattern?
50. What is the concept of callback?
51. What is a DPI call?
52. What is the difference between “DPI import” and “DPI export”?
53. What are system tasks and functions? Give some example of system
tasks and functions with their purpose.
54 What is the difference between $rose and @ (posedge) ?
55. What is the Difference between param and typedef?
56 What is difference between queue and mailbox?
57 How to check if any bit of the expression is X or Z?
58 What is extern ?
59 what is Layred Test Benches ?