What does a design verification engineer do?

Design Engineer : The responsibility of logic design Er is to implement architecture given by architect . For better design , design engineer puts much effort on bug free quality design, less number of logic gates which implements the design, so that it will have low power consumption. Most of design have clock disable feature , so designer roles to implement in smart manner so that have less power consumption.Designer has to produce design document which is used for verification.

Verification Engineer Role : Verify the architecture implemented logic design, focus on bug free design , smart random input , designing reference model which will be used to test design.Write Testbench which is more configurable, reusable. Read Design document and map the port to your TB and verify the functionalities.

Verification is done at many level before selling into market

Unit Level : Testing of unit ensuring it works fine and Testbench is reconfigurable ,mainly UVM/Fusion/OVM/VMM are used to do so

Subsystem/System : it is like SOC verifcation where many units are sitting together , you should know the architecture details of all those units, and know the design ios to do verification

Emulation : Dump the code in FPGA kind of model , it will be in hardware , which will be very fast , generally used for soc verification

Post silicon : Run your actual hardware and see its working , how does it work , run operating system on it , see whether it is butting up or not , once it boots up see read write functions , see how performance parameter , tune it , find out if there are any bugs into it, if yes ,ask to reproduce at other level of verification , re run , re design..

There are two type of verification

Functional verification : Random state space , when you verifying through functional verification , you don’t cover each state , you cover critical state space , where you think the chances of bus are more.

Formal Verification : Whole state space is verified , you cover all input of design , if there are n input you have input 2^n input combination to verify the design

so for every level of verification , generally it is handled by different team , but purpose remains same