What is equivalent checking in VLSI?

In VLSI equivalent checking means you have check logic design against the final  net-list , net-list is generated by DRC rule and timing analysis. In case of mismatch either in timing re design is done some time or optimization is done in net-list to avoid mismatch.

It can be done by formal equivalence check  property , formal exhaustively covers all possible scenarios ,it is used in many companies to do so .

In net-list functionality is checked , net-list has to go montocarlo simulation test which enables different temperature testing , different pressure scenarios testing. In real chip it has to perform under different environment.