Why gate simulation is needed even though STA (static time analysis ) is done?
Companies Related Questions, Functional Verification 0 CommentsThere are few things which is very important now a day which leads to have gate simulation.
1 Logic designs are not fully synchronous , for testing asynchronous design , gate level simulation models it accurately.
2. to check power up/reset operation of logic design.
3 to check x propagation testing , if there is non availability synchronizers it may propagate X.
4 To model real glitches at the edge because of combinational design
5 to catch multicyle path in presence of such test
6 To verify if design works at the desired frequency with actual delays in place