Companies Related Questions, UVM 0 Comments

m_sequencer  is default sequencer and p_sequncer is typecast to m_sequencer in other words m_sequencer is a handle of type uvm_sequencer_base which is available by default in a sequence. p_sequencer :The real sequencer on which a sequence is running would normally be derived from the uvm_sequencer_base class.Hence to access the real sequencer on which sequence is

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Computer Archtecture 0 Comments

Different Computer Architectures in Market 1 X86 Architecture(intel) Architecture :It is based on 8086 architecture initially, x86 came as a name because many successors of the architecture ends with “86“. It is CISC based architecture. Many Well-known processor from intel and AMD uses this architecture like Pentium Series AMD Athlon Intel Haswell and Broadwell series 2 Power Architecture (IBM):it is developed by IBM, It is

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Companies Related Questions, System Verilog 0 Comments

Yes , Answer to this question is take help of assign keyword and assign the one module signal to another module signal based on condition passed through config files Lets see how can you do it assign x.y_signal= sknobs::get_string(“+a.b.c.d.e.config=rtl”,”rtl”) == “rtl” ? ‘h0 : a.b.c.d.signal_dest;  

Companies Related Questions, System Verilog 0 Comments

Example 1 // Code your testbench here // or browse Examples module poly_case1; class BaseC; virtual function void func1; $display (“func1 in BaseC”); endfunction endclass: BaseC class DerivedC extends BaseC; function void func1; $display (“func1 in DerivedC”); endfunction endclass : DerivedC BaseC P1 ; DerivedC P2 = new; initial begin P1 = P2; P1.func1; end

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Career Oppurtunity, Companies Related Questions , 0 Comments

For verification engineer the toughest task is make testplan which captures all the features to tested. When we say features to tested , verification engineers to read the specs carefully and make note of all features. Now to know the features has been tested for certain scenario, verification engineer need to write coverage. When coverage

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Career Oppurtunity , 0 Comments

Though there are many website which talks about design and verification in VLSI , we will through one bye one 1 https://verificationacademy.com/ , has many videos on following topics which covers  many topics like , by clicking on these , you can access it. verification academy needs user registration, prior of accessing these material , you 

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Companies Related Questions, Computer Archtecture , , 0 Comments

This is more basic questions on Computer Architecture … This section mainly deals with memory part and we will few question memory like RAM, ROM , virtual memory , DDR. So lets start one by one 1. Define Memory Access Time? Answer : It is the time taken by the memory to supply the contents

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Companies Related Questions, Computer Archtecture 0 Comments

1. What are the basic steps required to execute an instruction by the processor? The basic steps required to execute an instruction by the processor are: i) Fetch the contents of the memory location pointed to by the PC. They are loaded into the IR. IR <- [PC] (ii) Assuming that the memory is byte

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Companies Related Questions, Computer Archtecture 0 Comments

A special control unit is provided to allow transfer of a block of data directly between an external device and the main memory, without continuous intervention by the processor. This approach is called direct memory access, or DMA. DMA transfers are performed by a control circuit that is part of the I/O device interface. We

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