Hardware Design and Verification
1 EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog, VHDL, C++/SystemC, and other HDLs. All you need is a web browser. The goal is to accelerate learning of design/testbench development with easier code sharing and simpler access to EDA tools and libraries, you can access here link 2 tutorial point verilog section ,
Magic, the VLSI layout editor, extraction, and DRC tool link XCircuit, the circuit drawing and schematic capture tool link IRSIM, the switch-level digital circuit simulator link Netgen, the circuit netlist comparison (LVS) and netlist conversion tool link Qrouter, the over-the-cell (sea-of-gates) detail router link Qflow, a complete digital synthesis design flow using open-source software and
How do we move from given specification to sign off for hardware Logic designer writes the specification for given design. Verification engineer goes through the specification provided by logic designer. He/She makes verification plan for the given specification of the logic design. Next step is to develop testbench. After developing testbench , it has to
Embedded is something which revolves around how to use an IC, where all the specs and properties and per defined and you cannot modify it. You have to just use IC as per your need. VLSI is something revolves around how to create an IC. Here you are the one who describe the functionality of IC. Even
Well computer architecture can be learned by following sites 1 Coursera , a course from priceton university by David Wentzlaff , you can enroll for course. link( : https://www.coursera.org/learn/comparch), click 2 NPTEL , a course from IIT Delhi by Dr. Smruti R. Sarangi , you can access his contents freely link (: https://onlinecourses.nptel.ac.in/noc18_cs29/preview) click 3. Youtube, a
Verification is process of ensuring specifications/features of hardware are matched as per the intend. So to ensure verification of chip, there are many level of verification are done Like, IP verification subsystem verification Full System Verification and to do verification there are few methodologies are available like 1 SIMULATION 2 EMULATION 3 FPGA prototype In
For verification engineer the toughest task is make testplan which captures all the features to tested. When we say features to tested , verification engineers to read the specs carefully and make note of all features. Now to know the features has been tested for certain scenario, verification engineer need to write coverage. When coverage
Though there are many website which talks about design and verification in VLSI , we will through one bye one 1 https://verificationacademy.com/ , has many videos on following topics which covers many topics like , by clicking on these , you can access it. verification academy needs user registration, prior of accessing these material , you
Design Engineer : The responsibility of logic design Er is to implement architecture given by architect . For better design , design engineer puts much effort on bug free quality design, less number of logic gates which implements the design, so that it will have low power consumption. Most of design have clock disable feature ,
