Hardware Design and Verification
Question asked write a constraint if address is within 100K it can have x1 and y1 state , if it goes beyond that it will have z1 state, if it x1 state it can have good and bad state otherwise it will idle state write a logic if class is instantiated n1 times , counter
what is difference between uvm_config_db and uvm_resource_db ? where we use task in uvm phases? difference between posedge and rise ? what is property in assertion ? what will be output of below code fork add(2,3); #10 add(3,3); join task add(int a, int b) int c = a +b; display(“a= %0d, b=%0d, c=%0d”, a,b,c); endtask
Section A : Complete Digital Basics Section B 1. Difference between rand and randc ? 2. What are the uvm phases uses in monitor/ sequencer/sequence ? 3.How to generate random values with probability ? like 1-8 with 80 % probability 0,15 with 20 % probability ? 4. Why there are phases in uvm /ovm ?
Q What is difference between write-thru and write-back caches? What are the advantages and disadvantages? Write Thru Cache: In a write-thru cache, every write operation to the cache is also written to the main memory. This is simple to design as memory is always up to date with respect to cache, but comes with the
Architecture Questions ============= 1. Mesi protocol,directory structure 2. Pipleline hazards 3. Memory organization/y we need cache 4. Cache coherancy 5. Branch Predictions 6. Transactional Memory 7. Slbie 8. Translation 9. Virtual address/real /Pysical 10. Types of cache set associative like that 11. Out of oreder Execution 12. Register 5 13. Risc vs Cisc 14. Caches
