Hardware Design and Verification
Cache is small memory which is very fast in access , so when processor want to access the data it tries to find out in cache , if it is found then it is known as cache hit and in case of not found , it is known as cache miss. In most of
Why it is used ? Virtual memory is used to increase the apparent size of the physical memory. Data are addressed in a virtual address space that can be as large as the addressing capability of the processor. But at any given time, only the active portion of this space is mapped onto locations in
1.Requires less registers therefore it is easier to design where in Cisc it is more expensive to make compared to RISC 2. Risc :Faster than CISC , Cisc is slower chips when performing instructions where 3. Risc : Reduced Instruction Set Computer CISC : Complex Instruction Set Architecture 4 Pipelining can be implemented easily , where
Exceptions and interrupts are unexpected events that disrupt the normal flow of instruction execution, when it occurs following things happens move the current PC into another register, call the EPC record the reason for the exception in the Cause register automatically disable further interrupts or execptions from occuring, by left-shifting the Status register change control (jump) to a hardwired exception handler
What are the types of cache misses? and how can we improve each type of miss? What is virtual memory, why do we use it. ? what is virtualisation ? What is TLB ? What is the principle of locality? What is functionality of MMU ? Find the tag bits size for set associative addressing
Difference between AHB and AXI? Difference between AXI3 and AXI4? What is AXI Lite? Name five special features of AXI? Why streaming support,it’s advantages? Write an assertion on handshake signals ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transaction What is the AXI capability of
AMBA AHB – Arbitration Questions 1.When should a master assert and deassert the HLOCK signal for a locked transfer? The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at
First One need to calculate no of block in cache, by dividing the total cache size by each cache line size and then no of sets is evaluated by dividing no of block by x (x is way set associative ) index bit : no of bit used to represent each cache line size remaining
Q What is difference between write-thru and write-back caches? What are the advantages and disadvantages? Write Thru Cache: In a write-thru cache, every write operation to the cache is also written to the main memory. This is simple to design as memory is always up to date with respect to cache, but comes with the
