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What is the need of clocking blocks ? In Verilog, the communication between blocks is specified using module ports. SystemVerilog adds the interface, a key construct that encapsulates the communication between blocks, thereby enabling users to easily change the level of abstraction at which the intermodule communication is to be modeled. An interface can specify

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An assertion is a description of a property of the design as per specification and is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening

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If coverage metric shows high code coverage and a low functional coverage then one or more of following possibilities could be the cause: 1) Not all functionality is implemented in the design as per the specification. Hence the code for same is missing while functional coverage metrics exists with no test 2) There could be

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What is coverage ? Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of

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implication operator as it name suggest it is something related to “the conclusion that can be drawn from something” same thing is valid for system verilog as well where can you use in SV , it will be used where you want certain things you want to constraint certain things based on certain value/expression/signal consider

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When the size of the collection is unknown or the data space is sparse, an associative array is used, which does not have any storage allocated until it is used. That means, it is dynamically allocated, but has non-contiguous elements. Associative array’s index expression is not restricted to integral expressions, but can be of any

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