Hardware Design and Verification
How many parallel processes does this code generate? fork for (int i=0; i < 10; i++ ) begin ABC(); end join Since the “for” loop is inside the fork join, it executes as a single thread. Which keyword in SystemVerilog is used to define Abstract classes? Sometimes a class is defined with an intention to
What is extern ? extern qualifier indicates that the body of the method (its implementation) is to be found outside the class declaration. before the method name, class name should be specified with class resolution operator to specify to which class the method corresponds to. Example-1: In the example below, creating the object of virtual class
What is the difference between new() and new[] in SystemVerilog? The function new() is the class constructor function in SystemVerilog. It is defined in a class to initialize data members of the class. The new[] operator is used to allocate memory for a dynamic array. The size of the dynamic array that needs to be
UVM config DB The configuration database provide access to a centralized database where type specific information can be stored and received. config_db can contain scalar objects, class handles, queues, lists, or even virtual interfaces. The database has both a name table and a type table and each resource is entered into both. Resources are stored
What is the difference between a reg, wire and logic in SystemVerilog? reg and wire are two data types that existed from Verilog, while logic is a new data type that was introduced in SystemVerilog. 1) A wire is a data type that can model physical wires to connect two elements. Wires can only be
What are different types of assertions? What are the differences between Immediate and Concurrent assertions? What is the difference between simple immediate assertion and deferred immediate assertions? What is the difference between simple immediate assertion and deferred immediate assertions? What are the advantages of writing a checker using SVA (SystemVerilog Assertions) as compared to writing
1. What is the difference between a reg, wire and logic in SystemVerilog? 2. What is the difference between a bit and logic data type? 3. What is the difference between logic[7:0] and byte variable in SystemVerilog? 4. Which of the array types: dynamic array or associative array, are good to model really large arrays,
