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m_sequencer  is default sequencer and p_sequncer is typecast to m_sequencer in other words m_sequencer is a handle of type uvm_sequencer_base which is available by default in a sequence. p_sequencer :The real sequencer on which a sequence is running would normally be derived from the uvm_sequencer_base class.Hence to access the real sequencer on which sequence is

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When the size of the collection is unknown or the data space is sparse, an associative array is used, which does not have any storage allocated until it is used. That means, it is dynamically allocated, but has non-contiguous elements. Associative array’s index expression is not restricted to integral expressions, but can be of any

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Functional Verification, System Verilog, UVM 0 Comments

What is memory  Memory is electronic component which can store information. it stores at certain address while reading from memory it retrieve the data from certain memory  Block Diagram of Memory DUT module memory #( parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 64 ) ( input clk, input reset, //control signals input [ADDR_WIDTH-1:0] addr, input wr_en,

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Functional Verification, Soc(System on Chip), System Verilog, UVM 0 Comments

Definition : Fifo (synchronous )  The Synchronous FIFO has a single clock port for both data-read and data-write operations, it means it is used for synchronising across two process  when two process are running on same clock.  One source writes to the FIFO and the other sources reads out the FIFO where it sees the  order

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