Functional Verification

Functional Verification is also known as Simulation


  • A “random walk” through the state space of the design
  • Scalable: applicable to designs of any size
  • Very robust set of tools & methodologies available for this technique

–Constraint-based stimulus generation; random biasing

–Clever testcase generation techniques

  • Explicit one-state-at-a-time nature severely limits attainable coverage

–Suffers the coverage problem: often fails to expose every bug

So Lets go through some UVM infrastructure to do the verification of different component


Normal Adder UVM verification : Click Here 

FIFO Verification Click Here

Memory verification: Click here