What is the advantage of UVM over systemverilog?

UVM is built on system verilog , so what ever UVM is doing underlying coding is SV

So in general , lets take broader view with respect to ther language

if you have heard of JAVA , and Hibernate

Hibernate : is a framework built on java helps in managing data base beautifully , if you have to change your data base from sql to oracle .. or anything, one place change will change you data base setup..

So UVM is something similar , it is framework , set of SV files, package.

Helps to solve many issue

so now SV is used to for design and verification

There were some problem in SV ,

Like

Re usability was less in SV , how can you re use your code frequently

can you have better synchronization mechanism for different state , like build , run ..

can you override you dv class dynamically

if you have to copy , compare ../ from class to other , you have to write the copy function ,compare .. can some one take care of these problem

can we have better communication between two file for sending messages

can we have Independency on Test case writer and testbench writer ??

People were using their in house methodology like OVM/VMM .././ to resolve such issues

but how could it common stuff to resolve such issue , then they came came with UVM

Yes UVM solve such issues