What is the difference between synthesis and simulation in verilog?

What do you mean by synthesis : The RTL code which is synthesizable which can be implemented in hardware, when you write any logic design, it has to be synthesizable, it should implement in terms of logic gates

There are many tool which does synthesis , it gives the idea of pre fabricated hardware in terms of logic gates which implement the desire behavior

Lets take an example

fork join are not synthesizable code

=== is not synthesizable code

if /else are synthesizable code

for more read : Synthesizable and Non-Synthesizable Verilog constructs

Now what next you asked about

Simulation : The execution of model , it could be your testbench, where reference model, TB need not be synthesizable, you try to find out bugs,expected result and see the behavior of task , for this also there are many EDA vendor who provides tool for it