Frequently asked question on verilog 1

QHow many flip-flops will be needed when following two codes are synthesized?

1) always @(posedge clk)

begin B = A;

C = B; end

2) always @(posedge clk) begin

B <= A;

C <= B;

end

Answer:

In first case, blocking assignments are used and hence the value of A will be assigned to B and the new value will be reflected onto C in same cycle and hence the variable B and C results in a wire. So, only one flip flow will be needed. In second case, old value of B is sampled before the new value is reflected in each cycle. Hence value of A reflects to C only in 2 cycles, resulting in two flip-flops.

Q Write a verilog code to swap contents of two registers (A and B) without any temporary register?
Ans:

Using a nonblocking assignment will swap the two values as shown below:

always @(posedge clk) begin

A<=B;

B<=A;

end

Q Write a Verilog module for the 3:1 multiplexer that uses the “?:” (conditional operator)

Ans
A 3:1 multiplexer has 3 input lines, 2 select lines and an output line which is driven by one of input lines based on select inputs.
module mux31_2(inp0,inp1,inp2,sel0,sel1, outres);

input inp0, inp1, inp2, sel0, sel1;

output outresult;

assign outresult = sel1 ? inp2 : (sel0 ? inp1 : inp0);

endmodule

QWhat is the difference between synchronous and asynchronous reset and how do we model synchronous and asynchronous reset using verilog code?

Ans

A reset is used to force the state of a design to a known condition after powering up. If a design samples reset on an edge of clock, then it is called as synchronous reset. If the design samples the reset signal without any clock then it is called an asynchronous reset. In terms of implementation, following coding style is used for a synchronous reset

always @ (posedge clk) begin

if (reset) begin

ABC <=0;

end

end

Following coding style is used for an asynchronous reset wherein the reset has highest priority and can happen even without a clock.

always @ (posedge clk or posedge reset ) begin

if (reset) begin

ABC <=0;

end

end