Frequently asked question on verilog 2

Q What is the difference between “==” and “===” operators?

Ans : Both of these are equality or comparison operators. The “==” tests for logical equality for two states (0 and 1), while the “===” operator tests for logical equality for four states (0,1, X and Z) If “==” is used to compare two 4-state variables (logics) and if at least one of them has an X or Z, the result will be X. If the “===” is used to compare two 4-state variables, then comparison is done on all 4 states including X and Z, and the result is 0 or 1.

QIf A and B are two 3-bit vectors initialised as follows: A = 3‘b1x0 B = 3‘b1x0

What would be value of following?

1) A==B

2) A===B

Ans :

1) A==B will only compare non-X/Z values and hence will result in an output “X” if any of the operands has an unknown bit 2) A===B will compare bits including X and Z and hence the comparison would return a 1 as both bit 1 are X for A and B.

Q Write verilog code for a flip-flop and latch and explain differences?

Ans :

For a flip-flop, the output changes only on the rising or falling edge of a clock signal even if input signal changes in between. However for a latch the output changes as soon as input changes provided the enable signal is high.

Following is the Verilog code for a D flip-flop with synchronous reset.

always @ (posedge clk) begin

if(reset) begin Q <= 0;

Qbar <= 1;

end

else begin

Q <= D;
Qbar <= ~D;

end

end
Following is the Verilog code for a latch with an enable.
always @ (D or Enable) begin

if(Enable) begin

Q <= D;

Qbar <= ~D;

end

end