What is polymorphism in system verilog ??
Companies Related Questions, System Verilog 0 CommentsPoly in means , means a same thing is known by different name
Lets take a example here
class Animal;
virtual function AnimalType();
$display(“ Welcome to Type Animal”);
endfunction
endclass
class Dog extends Animal;
function AnimalType();
$display(“Welcome to Dog Animal Type”);
endclass
class Cat extends Animal;
function AnimalType();
$display(“Welcome to Cat Animal Type”);
endclass
class Horse extends Animal;
function AnimalType();
$display(“Welcome to Horse Animal Type”);
endclass
program
main
AnimalType ET;
Dog D1;
Cat C1;
Horse H1;
initial
begin
ET= new();
ET.AnimalType();
D1= new();
ET= D1;
ET.AnimalType();
C1= new();
ET=C1;
ET.AnimalType();
H1= new();
ET=H1;
ET.AnimalType();
end
endprogram
what would be result
Welcome to Type Animal
Welcome to Dog Animal Type
Welcome to Cat Animal Type
Welcome to Horse Animal Type
what did you see here same Animal Type class have different output , it means same things represented in many form , hope it helps you to understand polymorphism
So polymorphism is concept of OOP , now use of this depends on such functionality requirement
polymorphism is achieved by declaring function/ task as a virtual