Write uvm sequence item for asynchronous fifo ??
Companies Related Questions, Functional Verification, System Verilog, UVM 0 CommentsBLOCK DIAGRAM
class seqItem extends uvm_sequence_item;
`uvm_object_utils(seqItem)
logic [8-1:0] rdata;
logic wfull;
logic rempty;
rand logic [8-1:0] wdata;
logic winc, wrst_n;
logic rinc, rrst_n;
function new (string name=”seqItem”);
super.new(name);
endfunction
endclass