Frequent Computer Architecture asked in hardware(hw) companies ?

What are the types of cache misses? and how can we improve each type of miss?
What is virtual memory, why do we use it. ?
what is virtualisation  ?
What is TLB ?
What is the principle of locality?
What is functionality of MMU ?
Find the tag bits size for set associative addressing ?
How many bits to implement LRU in a 4 way associative cache?
Describe a program/algo (say in C) to find the L1 cache size of your underlying hardware. No parameters given like associativity, block size etc. You  also do not have any mechanism that tells you if your cache missed or hit in the underlying hardware
Describe a memory access pattern that never misses in the cache ?
If I say your cache size is 8KB, describe a program/algo that proves it is 8Kb ?
Explain  memory management how it manages ?
What are common techniques to speed up execution, higher IPC (Instruction per clock) ?
Differences and benefits of In order vs out of order execution, concept of Register renaming, branches and prediction?
Different are the Addressing modes ?
Directory vs snoop based protocols (MESI/MOESIF) comparison ?
Multi processor implementations ?
Interrupts and exceptions – differences, priority and handling of same ?
Memory ordering and consistency ?
Difference between cache coherency and cache consistency ?
Describe, in as much detail as possible, everything that happens on a Linux machine from the point when you hit the enter key after typing “./a.out” to the moment when “Hello World!” gets printed on the screen ?
Mention what are the different types of fields that are part of an instruction?
A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is ?
What technique is used to automatically move program and data blocks into the physical main memory when they are required for execution?
What is the use of RAID system?
How  DMA works ?
What is the importance of pipe lining in computer architecture?
What are the various pipeline hazards?
What are structural hazards in reference to pipelines?
What are data hazards in reference to pipelines?
How can data hazards be classified?
What are stalls in reference to pipeline hazards?
How can hazards be controlled?
What are branch prediction schemes?
What are Exceptions?
What are the different types of exceptions?
What are user maskable exceptions?
What is parallelism in reference to computer architecture?
What are the two different levels of parallelism?
What is instruction level parallelism?
What is dynamic scheduling?
What are crosscutting issues faced in ILP?
What are the limits of instruction level parallelism?
What do you understand by thread level parallelism?