What is the need of clocking blocks ?

What is the need of clocking blocks ?

In Verilog, the communication between blocks is specified using module ports. SystemVerilog adds the interface, a key construct that encapsulates the communication between blocks, thereby enabling users to easily change the level of abstraction at which the intermodule communication is to be modeled. An interface can specify the signals or nets through which a testbench communicates with a device under test (DUT). However, an interface does not explicitly specify any timing disciplines, synchronization requirements, or clocking paradigms.

SystemVerilog adds the clocking block that identifies clock signals and captures the timing and synchronization requirements of the blocks being modeled. A clocking block assembles signals that are synchronous to a particular clock and makes their timing explicit. The clocking block is a key element in a cycle-based methodology, which enables users to write testbenches at a higher level of abstraction. Rather than focusing on signals and transitions in time, the test can be defined in terms of cycles and transactions. Depending on the environment, a testbench can contain one or more clocking blocks, each containing its own clock plus an arbitrary number of signals. The clocking block separates the timing and synchronization details from the structural, functional, and procedural elements of a Testbench.

Thus, the timing for sampling and driving clocking block signals is implicit and relative to the clocking block’s clock. This enables a set of key operations to be written very succinctly, without explicitly using clocks or specifying timing. These operations are as follows:
— Synchronous events
— Input sampling
— Synchronous drives
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet.

These are links to learn about SV clocking blocks.
– Specify synchronization characteristics of the design
– Offer a clean way to drive and sample signals
– Provides race-free operation if input skew > 0
– Helps in testbench driving the signals at the right time
– Features
– Clock specification
– Input skew,output skew
– Cycle delay (##)
– Can be declared inside interface,module or program

Example :
01.Module Clocking (ck, enin, din, enout, dout);
02.input ck,enin;
03.input [31:0] din ;
04.output enout ;
05.output [31:0] dout ;
06.
07.clocking sd @(posedge ck);
08.input #2ns ein,din ;
09.output #3ns enout, dout;
10.endclocking:sd
11.
12.reg [7:0] sab ;
13.initial begin
14.sab = sd.din[7:0];
15.end
16.endmodule:Clocking