How to make test plan for any project for Verfication?

For verification engineer the toughest task is make testplan which captures all the features to tested. When we say features to tested , verification engineers to read the specs carefully and make note of all features.

Now to know the features has been tested for certain scenario, verification engineer need to write coverage.

When coverage is captured for certain scenario, is checker in the place ?, So checker has to there for different features testing.

We will see couple of example for making testplan

Lets See The Fifo(Synchronous) Testplan

Scenario:

DUT 

A Synchronous FIFO has a single clock port for both read and write operations.

The Data driven on the data-input port (DIN) is written into the next available empty FIFO location on a rising clock edge when the write-request input (WRITE) is high. This is also known as a PUSH operation on FIFO. Data can be read out of the FIFO via output port (DOUT) in the order in which it was written by asserting read-request (READ) prior to a rising clock edge.

The FIFO full status output flag (FULL) indicates that no more empty locations remain in the internal array.

The FIFO empty status output flag (EMPTY) indicates that all locations inside the FIFO are empty. The FIFO status cannot be corrupted by invalid requests. Requesting a read operation while the EMPTY flag is active will not cause any change in the current state of the FIFO. Similarly, a write operation while the FULL flag is active will not cause any change in the current state of the FIFO.

The RESET signal clears internal control logic and the status flags.

FIFO its depth is 32 and width is 16 bits.

Testplan

1 Reset Case 

When the FIFO is reset, the FIFO empty flag should be set and the full flag should be reset.

2 Non Reset Case

Fifo Full Scenario

If the fifo word counter  is greater than 31, the FIFO is full

If the fifo word counter  is less than 32, the FIFO is not full

if fifo counter is 31 , and there is write operation fifo will be full

Fifo Empty Scenario

if fifo counter is 1 , and there is readoperation fifo will be empty, empty flag should  be set

when fifo is reset, the empty flag should be set

Normal Scenario

Write to n locations , read it back, check data is matching or not

Simultaneous  read and write