Hardware Design and Verification
Difference between AHB and AXI? Difference between AXI3 and AXI4? What is AXI Lite? Name five special features of AXI? Why streaming support,it’s advantages? Write an assertion on handshake signals ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transaction What is the AXI capability of
1. Why is there no wait signal on the APB? The APB has been designed to implement as simple an interface as possible. Having this simple design makes it much easier to connect new APB peripherals and makes the analysis of the system performance easier to calculate. Although many APB peripherals are slow devices, such
1. The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed? For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot ROM which is only ever accessed at initial power upcould insert a larger number of
AMBA AHB – Arbitration Questions 1.When should a master assert and deassert the HLOCK signal for a locked transfer? The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at