Hardware Design and Verification
1 How To Start Virtual Sequencer ? Answer : click 2 What Is M_sequencer And P_sequencer ? Answer : click 3 Write Uvm Sequence Item For Asynchronous Fifo ?? Answer : click 4 What Is Virtual Sequencer ? When And How To Use It ? Answer : click 5 What Is Difference Between UVM Resource DB Vs UVM Config Db
Here are few questions which are tricky to solve System Verilog Questions 1 Implement randc function using rand in system verilog ? Answer : click 2 Write A System Verilog Constraint To Generate Unique Values In Array Without Unique Keyword Answer : click 3 Fork Join Tricky Example Answer : There are few type of fork join questions
How do you implement randc function using rand in system verilog ? Program : Understand the difference between randc and rand function rand : it is random number , it can be repeated. randc : it is random number with no repetition for a cycle. it may repeat once it complete one cycle. Lets
Consider a situation in which two processors in an SMP configuration, over time, require access to the same line of data from main memory. Both processors have a cache and use the MESI protocol. Initially, both caches have an invalid copy of the line. If this is the start of a sequence of accesses, draw
There are few things which is very important now a day which leads to have gate simulation. 1 Logic designs are not fully synchronous , for testing asynchronous design , gate level simulation models it accurately. 2. to check power up/reset operation of logic design. 3 to check x propagation testing , if there is
UVM test benches .. I tried covering few example , go through each Memory UVM testbench UVM testbench click here Synchronous FIFO UVM TESTBENCH UVM Testbench click here NORMAL ADDER UVM Tesbench UVM Testbench click here
A virtual sequencer is a sequencer that can run sequences, but it doesn’t connect to any drivers,hence the virtual name. It is designed to run virtual sequences that spawn sub-sequences on other sequencers. 1 You can start virtual sequences on a virtual sequencer. 2 Handles part of the virtual sequence can be started on null
module unique_array; class data; rand bit [7:0] data[]; constraint data_values { foreach(data[i]) foreach(data[j]) if(i != j) data[i] != data [j] ;} endclass data cl_ob; initial begin cl_ob = new(); cl_ob.data = new[5]; assert(cl_ob.randomize()); foreach(cl_ob.data[i]) $display(“%d”,cl_ob.data[i]); end endmodule
Lets write some code module fork_test; initial begin for (int j=0; j<3; j++) begin fork $display(j); join_none end end endmodule Output 3 3 3 It outputs 3 because there is only one variable j shared by all the threads, and its value is 3 before any of the threads start executing. None of the
How do we move from given specification to sign off for hardware Logic designer writes the specification for given design. Verification engineer goes through the specification provided by logic designer. He/She makes verification plan for the given specification of the logic design. Next step is to develop testbench. After developing testbench , it has to
