Hardware Design and Verification
This is tricky and generally we get confuse and think that req |-> ##[1:$] ack ; will give the correct result but this is not true The solution for this issue is module req_ack_sequential_checker(input bit clk,input bit req,input bit ack);bit error_flag ; // Error flag to indicate a protocol violationbit last_req_acknowledged ; // Flag to
Here are few questions which are tricky to solve System Verilog Questions 1 Implement randc function using rand in system verilog ? Answer : click 2 Write A System Verilog Constraint To Generate Unique Values In Array Without Unique Keyword Answer : click 3 Fork Join Tricky Example Answer : There are few type of fork join questions
How do you implement randc function using rand in system verilog ? Program : Understand the difference between randc and rand function rand : it is random number , it can be repeated. randc : it is random number with no repetition for a cycle. it may repeat once it complete one cycle. Lets
module unique_array; class data; rand bit [7:0] data[]; constraint data_values { foreach(data[i]) foreach(data[j]) if(i != j) data[i] != data [j] ;} endclass data cl_ob; initial begin cl_ob = new(); cl_ob.data = new[5]; assert(cl_ob.randomize()); foreach(cl_ob.data[i]) $display(“%d”,cl_ob.data[i]); end endmodule
Lets write some code module fork_test; initial begin for (int j=0; j<3; j++) begin fork $display(j); join_none end end endmodule Output 3 3 3 It outputs 3 because there is only one variable j shared by all the threads, and its value is 3 before any of the threads start executing. None of the
Yes , Answer to this question is take help of assign keyword and assign the one module signal to another module signal based on condition passed through config files Lets see how can you do it assign x.y_signal= sknobs::get_string(“+a.b.c.d.e.config=rtl”,”rtl”) == “rtl” ? ‘h0 : a.b.c.d.signal_dest;
Example 1 // Code your testbench here // or browse Examples module poly_case1; class BaseC; virtual function void func1; $display (“func1 in BaseC”); endfunction endclass: BaseC class DerivedC extends BaseC; function void func1; $display (“func1 in DerivedC”); endfunction endclass : DerivedC BaseC P1 ; DerivedC P2 = new; initial begin P1 = P2; P1.func1; end
Differences 1. The most obvious one : Initial blocks get executed at the beginning of the simulation, final block gets executed at the end of simulation 2. Final block has to be executed in zero time, which implies it can’t have any delay, wait, or non-blocking assignments. Initial block doesn’t have any such restrictions of
With inheritance we are able to force a subclass to offer the same properties like their superclasses. Consequently, objects of a subclass behave like objects of their superclasses. Sometimes it make sense to only describe the properties of a set of objects without knowing the actual behaviour beforehand Abstract classes are those which can be
An interface encapsulate a group of inter-related wires, along with their directions (via modports) and synchronization details (via clocking block). The major usage of interface is to simplify the connection between modules. But Interface can’t be instantiated inside program block, class (or similar non-module entity in SystemVerilog). But they needed to be driven from verification