Hardware Design and Verification
Q What is the difference between “==” and “===” operators? Ans : Both of these are equality or comparison operators. The “==” tests for logical equality for two states (0 and 1), while the “===” operator tests for logical equality for four states (0,1, X and Z) If “==” is used to compare two 4-state
QHow many flip-flops will be needed when following two codes are synthesized? 1) always @(posedge clk) begin B = A; C = B; end 2) always @(posedge clk) begin B <= A; C <= B; end Answer: In first case, blocking assignments are used and hence the value of A will be assigned to B
Verilog language supports two types of assignments: blocking and nonblocking. In blocking assignments, evaluation and assignment happens immediately. Thus, if there are multiple blocking assignments in a sequential block, each statement execution follows in a blocking way as shown below. always @(posedge clk) begin x = a|b; y = a&b; z = x|y; end In