Example of Polymorphism in system verilog
Companies Related Questions, System Verilog 0 CommentsExample 1
// Code your testbench here
// or browse Examples
module poly_case1;
class BaseC;
virtual function void func1;
$display (“func1 in BaseC”);
endfunction
endclass: BaseC
class DerivedC extends BaseC;
function void func1;
$display (“func1 in DerivedC”);
endfunction
endclass : DerivedC
BaseC P1 ;
DerivedC P2 = new;
initial begin
P1 = P2;
P1.func1;
end
endmodule
Output
func1 in DerivedC
Example 2
module poly_case2;
class BaseC;
virtual function void func1;
$display (“func1 in BaseC”);
func2;
endfunction
function void func2;
$display (“func2 in BaseC”);
endfunction
endclass: BaseC
class DerivedC extends BaseC;
function void func1;
$display (“func1 in DerivedC”);
func2;
endfunction
function void func2;
$display (“func2 in DerivedC”);
endfunction
endclass : DerivedC
BaseC P1 ;
DerivedC P2 = new;
initial begin
P1 = P2;
P1.func1;
end
endmodule:poly_case2
output
func1 in DerivedC
func2 in DerivedC