UVM Questions

Questions
What are some of the benefits of UVM methodology?
What are some of the drawbacks of UVM methodology?
What is the concept of Transaction Level Modelling?
What are TLM ports and exports?
What are TLM FIFOs?
What is the difference between a get() and peek() operation on a TLM ?
What is the difference between a get() and try_get() operation on a TLM
fifo?
What is the difference between analysis ports and TLM ports? And what is the difference between analysis FIFOs and TLM FIFOs? Where are the analysis ports/FIFOs used?
What is the difference between a sequence and sequence item?
What is the difference between a uvm_transaction and a uvm_sequence_item?
Explain the concept of Agent in UVM methodology.
What all different components can a UVM agent have?
What is the difference between get_name() and get_full_name()
How is ACTIVE agent different from PASSIVE agent?
How is an Agent configured as ACTIVE or PASSIVE?
What is a sequencer and a driver, and why are they needed?
What is the difference between a monitor and a scoreboard in UVM?
Which method activates UVM testbench and how is it called
What steps are needed to run a sequence?
Explain the protocol handshake between a sequencer and driver?
What are pre_body() and post_body() functions in a sequence? Do they
always get called?
Is the start() method on a sequence blocking or nonblocking?
What are the different arbitration mechanisms available for a
Sequencer?
How do we specify the priority of a sequence when it is started on a sequencer?
How can a sequence get exclusive access to a sequencer?
What is the difference between a grab() and a lock() on sequencer?
What is the difference between a pipelined and a non-pipelined sequence-driver model?
What is the difference between a pipelined and a non-pipelined sequence-driver model?
How do we make sure that if multiple sequences are running on a sequencer-driver, responses are send back from driver to the correct sequence?
What is m_sequencer handle?
What is a p_sequencer handle and how is it different in m_sequencer?
What is the difference between early randomization and late randomization while generating a sequence?
What is a subsequence?
What is the difference between get_next_item() and try_next_item()
What is the difference between get_next_item() and get() methods in UVM driver class?
What is the difference between get() and peek() methods of UVM driver class?
What is the difference in item_done() method of driver-sequencer API when called with and without arguments?
Which of the following driver class methods are blocking calls and
which are nonblocking?
How can you stop all sequences running on a sequencer?
Which method in the sequence gets called when user calls sequence.print() method?
What is a virtual sequence and where do we use a virtual sequence? What are its benefits?
What is a factory?
What is the difference between creating an object using new() and
create() methods?
How do we register an uvm_component class and uvm_sequence class
with factory?
Why should we register a class with factory?
What is meant by factory override?
What is the difference between instance override and type override? NVDIA
Can instance override and type override be used for both UVM_component class and transaction types ?
Can instance override and type override be used for both UVM_component class and transaction types ?
What is the concept of objections and where are they useful?
How can we implement a simulation timeout mechanism in UVM methodology?
What is the concept of phasing in UVM methodology?
What are the different phases of a UVM component? What are the subphases for the UVM run_phase()?
Why is build_phase() executed top down in uvm_component hierarchy? General Interview Question
What is the use of phase_ready_to_end() method in a uvm_component class?
What is uvm_config_db and what is it used for? General Question
How do we use the get() and set() methods of uvm_config_db? General Question
Is it possible for a component lower in testbench hierarchy to pass a handle to a component in higher level of hierarchy using get/set config methods?
What is the recommended way of assigning virtual interfaces to different components in a UVM verification methodology?
Explain how simulation ends in UVM methodology?
What is UVM RAL (UVM Register Abstraction Layer)?
What is UVM Call back?
What is uvm_root class?
What is the parent class for uvm_test?