Cadence Questions

1. what is difference between uvm_config_db and uvm_resource_db ?
2. where we use task in uvm phases?
3. difference between posedge and rise ?
4. what is property in assertion ?
5. what will be output of below code

fork

add(2,3);

#10

add(3,3);

join

task add(int a, int b)

int c = a +b;

display(“a= %0d, b=%0d, c=%0d”, a,b,c);

endtask

6. what is difference between task and function  ?

7. what are uvm phases ?

8. what happens in each uvm phases ?

9. what is difference between logic and register ?

10 what are data type in system verilog ?

11 what are pipeline hazards ?

12. how program register will be designed for 32 bit register ?

13. how do we stop simulation in UVM ?

14 . how can we inject an error ?

15 what is uvm callback ?

16 . what is extern ?