System Verilog Assertion Questions

What are different types of assertions?
What are the differences between Immediate and Concurrent
assertions?
What is the difference between simple immediate assertion and deferred immediate assertions?
What is the difference between simple immediate assertion and deferred immediate assertions?
What are the advantages of writing a checker using SVA (SystemVerilog Assertions) as compared to writing it using a procedural SystemVerilog code?
What are the advantages of writing a checker using SVA (SystemVerilog Assertions) as compared to writing it using a procedural SystemVerilog
code?
What are the different ways to write assertions for a design unit?
What is a sequence as used in writing SystemVerilog Assertions?
Is there a difference
between $rose(tst_signal) and @posedge(tst_signal )?
Is it possible to have concurrent assertions implemented inside a class?
What is a sequence repetition operator? What are the three different type of repetition operators used in sequences?

Write an assertion check to make sure that a signal is high for a minimum of 2 cycles and a maximum of 6 cycles.
What is an implication operator?
What is the difference between an overlapping and non overlapping implication operator?
Can implication operator be used in sequences?
Are following assertions equivalent?
1) @(posedge clk) req |=> ##2 $rose(ack);
2) @(posedge clk) req |-> ##3 $rose(ack);
For a synchronous FIFO of depth=16, write an assertion for following
scenarios. Assume a clock signal (clk), write and read enable signals, full
flag and a word counter signal.
1) If the word count is >15, FIFO full flag is set.
2) If the word count is 15 and a new write operation happens without a
simultaneous read, then the FIFO full flag gets set.

Is nested implication allowed in SVA?
What does the system task $past() do?
Write an assertion checker to make sure that an output signal never
goes X?
Write an assertion to make sure that the state variable in a state machine is always one hot value.
Write an assertion to make sure that a 5-bit grant signal only has one bit set at any time? (only one req granted at a time)
Write an assertion which checks that once a valid request is asserted by the master, the arbiter provides a grant within 2 to 5 clock cycles
How can you disable an assertion during active reset time?
What’s the difference between assert and assume directives in
SystemVerilog?
What is bind construct used in SystemVerilog for?
How can all assertions be turned off during simulation?

What are the different ways in which a clock can be specified to a property used for assertion?