Question asked
- write a constraint if address is within 100K it can have x1 and y1 state , if it goes beyond that it will have z1 state, if it x1 state it can have good and bad state otherwise it will idle state
- write a logic if class is instantiated n1 times , counter value should be x1
- how will you test FIFO which will warp after 31 entry
- write an assertion in such way that if signal is 10 cycle earlier if it is high and x goes high
- what are UVM phases ?
- what are different phases used in monitor ?
- write a system verilog sequence ?
- what is polymorphism ? explains with example?
- what is p_sequencer and m_sequencer ?