Normal UVM adder Testbench

Well, Lets take adder of following specification :

it is one bit adder , one result , one bit carry 

So system verilog interface port definition will look like

interface dut_if1;
logic a_in, b_in, c_in;
logic sum_out;
logic carry_out;
logic clock,reset;
endinterface

So Lets go through definition of each component , click here to get details information about its architecture