What is an assertion and what are the benefits of using assertions in Verification?

An assertion is a description of a property of the design as per specification and is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening in the design and occurs during simulation, then also the assertion fails. Following are some of the benefits of using Assertions in Verification:

1) Assertions improve error detection in terms of catching simulation errors as soon a design specification is violated

2) Assertions provide better observability into design and hence help in easier debug of test failures.

3) Assertions can be used for both dynamic simulations as well as in formal verification of design

4) Assertions can also be used to provide functional coverage on input stimulus and to validate that a design property is infact simulated.