Companies Related Questions, System Verilog 0 Comments

What is coverage ? Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of

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Companies Related Questions, Formal Verification 0 Comments

1  What is Formal Verification? Formal Verification is a process where we use mathematical modelling to verify a Design implementation meets a specification. It uses mathematical reasoning and algorithms to prove that a design meets a specification. In formal verification, all cases (inputs and state) are covered implicitly by the tool without the need for

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AMBA, Companies Related Questions, Computer Archtecture 0 Comments

AMBA AHB – Arbitration Questions 1.When should a master assert and deassert the HLOCK signal for a locked transfer? The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at

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Companies Related Questions, Verilog 0 Comments

Verilog language supports two types of assignments: blocking and nonblocking. In blocking assignments, evaluation and assignment happens immediately. Thus, if there are multiple blocking assignments in a sequential block, each statement execution follows in a blocking way as shown below. always @(posedge clk) begin x = a|b; y = a&b; z = x|y; end In

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Career Oppurtunity, Companies Related Questions 0 Comments

Design Engineer : The responsibility of logic design Er is to implement architecture given by architect . For better design , design engineer puts much effort on bug free quality design, less number of logic gates which implements the design, so that it will have low power consumption. Most of design have clock disable feature ,

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Companies Related Questions, Functional Verification, System Verilog 0 Comments

implication operator as it name suggest it is something related to “the conclusion that can be drawn from something” same thing is valid for system verilog as well where can you use in SV , it will be used where you want certain things you want to constraint certain things based on certain value/expression/signal consider

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