Hardware Design and Verification
Section A : Complete Digital Basics Section B 1. Difference between rand and randc ? 2. What are the uvm phases uses in monitor/ sequencer/sequence ? 3.How to generate random values with probability ? like 1-8 with 80 % probability 0,15 with 20 % probability ? 4. Why there are phases in uvm /ovm ?
1. if we blackbox the design , will other part of design will get verified correctly ? 2. What are the engines used in formal ? 3. What are different technique used if design is not giving proof ? 4 . what are the component which can be re used in functional verification which was
Questions What are some of the benefits of UVM methodology? What are some of the drawbacks of UVM methodology? What is the concept of Transaction Level Modelling? What are TLM ports and exports? What are TLM FIFOs? What is the difference between a get() and peek() operation on a TLM ? What is the difference
Q What is difference between write-thru and write-back caches? What are the advantages and disadvantages? Write Thru Cache: In a write-thru cache, every write operation to the cache is also written to the main memory. This is simple to design as memory is always up to date with respect to cache, but comes with the
Architecture Questions ============= 1. Mesi protocol,directory structure 2. Pipleline hazards 3. Memory organization/y we need cache 4. Cache coherancy 5. Branch Predictions 6. Transactional Memory 7. Slbie 8. Translation 9. Virtual address/real /Pysical 10. Types of cache set associative like that 11. Out of oreder Execution 12. Register 5 13. Risc vs Cisc 14. Caches
1. What is the difference between a reg, wire and logic in SystemVerilog? 2. What is the difference between a bit and logic data type? 3. What is the difference between logic[7:0] and byte variable in SystemVerilog? 4. Which of the array types: dynamic array or associative array, are good to model really large arrays,
