Hardware Design and Verification
MESI and MOESI protocols Modified (M) – Cache line has been modified. It is different from main memory, and is the only cached copy. Owned (O) – Cache line is dirty and is possibly in more than one cache. A cache line in the Owned state holds the most recent, correct copy of the data. Only
This is more basic questions on Computer Architecture … This section mainly deals with memory part and we will few question memory like RAM, ROM , virtual memory , DDR. So lets start one by one 1. Define Memory Access Time? Answer : It is the time taken by the memory to supply the contents
1. What are the basic steps required to execute an instruction by the processor? The basic steps required to execute an instruction by the processor are: i) Fetch the contents of the memory location pointed to by the PC. They are loaded into the IR. IR <- [PC] (ii) Assuming that the memory is byte
A special control unit is provided to allow transfer of a block of data directly between an external device and the main memory, without continuous intervention by the processor. This approach is called direct memory access, or DMA. DMA transfers are performed by a control circuit that is part of the I/O device interface. We
This portion consists of the page table entries that correspond to the most recently accessed pages. A small cache, usually called the Translation Lookaside Buffer (TLB) is incorporated into the MMU for this purpose. The operation of the TLB with respect to the page table in the main memory is essentially the same as the
The process of translating a virtual address into physical address is known as address translation. It can be done with the help of MMU. A simple method for translating virtual addresses into physical addresses is to assume that all programs and data are composed of fixed-length units called pages, each of which consists of a
Cache is small memory which is very fast in access , so when processor want to access the data it tries to find out in cache , if it is found then it is known as cache hit and in case of not found , it is known as cache miss. In most of
Why it is used ? Virtual memory is used to increase the apparent size of the physical memory. Data are addressed in a virtual address space that can be as large as the addressing capability of the processor. But at any given time, only the active portion of this space is mapped onto locations in
1.Requires less registers therefore it is easier to design where in Cisc it is more expensive to make compared to RISC 2. Risc :Faster than CISC , Cisc is slower chips when performing instructions where 3. Risc : Reduced Instruction Set Computer CISC : Complex Instruction Set Architecture 4 Pipelining can be implemented easily , where
Exceptions and interrupts are unexpected events that disrupt the normal flow of instruction execution, when it occurs following things happens move the current PC into another register, call the EPC record the reason for the exception in the Cause register automatically disable further interrupts or execptions from occuring, by left-shifting the Status register change control (jump) to a hardwired exception handler
