Hardware Design and Verification
Differences 1. The most obvious one : Initial blocks get executed at the beginning of the simulation, final block gets executed at the end of simulation 2. Final block has to be executed in zero time, which implies it can’t have any delay, wait, or non-blocking assignments. Initial block doesn’t have any such restrictions of
With inheritance we are able to force a subclass to offer the same properties like their superclasses. Consequently, objects of a subclass behave like objects of their superclasses. Sometimes it make sense to only describe the properties of a set of objects without knowing the actual behaviour beforehand Abstract classes are those which can be
An interface encapsulate a group of inter-related wires, along with their directions (via modports) and synchronization details (via clocking block). The major usage of interface is to simplify the connection between modules. But Interface can’t be instantiated inside program block, class (or similar non-module entity in SystemVerilog). But they needed to be driven from verification
Unlike procedural programming, here in the OOP programming model programs are organized around objects and data rather than actions and logic. Objects represent some concepts or things and like any other objects in the real Objects in programming language have certain behavior, properties, type, and identity. In OOP based language the principal aim is to
What is the need of clocking blocks ? In Verilog, the communication between blocks is specified using module ports. SystemVerilog adds the interface, a key construct that encapsulates the communication between blocks, thereby enabling users to easily change the level of abstraction at which the intermodule communication is to be modeled. An interface can specify
Wire:- 1. Wires are used for connecting different elements 2. They can be treated as a physical wire 3. They can be read or assigned 4. No values get stored in them 5. They need to be driven by either continuous assign statement or from a port of a module Reg:- 1. Contrary to their
We can pass data member to any function. Now consider a case where you are passing a function (say func1) as a data member to another function (say func2) and you get what is called callback. The reason why it is called callback is that the function func2 now can call anywhere in its code
What are the types of cache misses? and how can we improve each type of miss? What is virtual memory, why do we use it. ? what is virtualisation ? What is TLB ? What is the principle of locality? What is functionality of MMU ? Find the tag bits size for set associative addressing
An assertion is a description of a property of the design as per specification and is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening
If coverage metric shows high code coverage and a low functional coverage then one or more of following possibilities could be the cause: 1) Not all functionality is implemented in the design as per the specification. Hence the code for same is missing while functional coverage metrics exists with no test 2) There could be
