1 What is Formal Verification? Formal Verification is a process where we use mathematical modelling to verify a Design implementation meets a specification. It uses mathematical reasoning and algorithms to prove that a design meets a specification. In formal verification, all cases (inputs and state) are covered implicitly by the tool without the need for
1. Why is there no wait signal on the APB? The APB has been designed to implement as simple an interface as possible. Having this simple design makes it much easier to connect new APB peripherals and makes the analysis of the system performance easier to calculate. Although many APB peripherals are slow devices, such
1. The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed? For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot ROM which is only ever accessed at initial power upcould insert a larger number of
AMBA AHB – Arbitration Questions 1.When should a master assert and deassert the HLOCK signal for a locked transfer? The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at
Q What is the difference between “==” and “===” operators? Ans : Both of these are equality or comparison operators. The “==” tests for logical equality for two states (0 and 1), while the “===” operator tests for logical equality for four states (0,1, X and Z) If “==” is used to compare two 4-state
QHow many flip-flops will be needed when following two codes are synthesized? 1) always @(posedge clk) begin B = A; C = B; end 2) always @(posedge clk) begin B <= A; C <= B; end Answer: In first case, blocking assignments are used and hence the value of A will be assigned to B
Verilog language supports two types of assignments: blocking and nonblocking. In blocking assignments, evaluation and assignment happens immediately. Thus, if there are multiple blocking assignments in a sequential block, each statement execution follows in a blocking way as shown below. always @(posedge clk) begin x = a|b; y = a&b; z = x|y; end In
Design Engineer : The responsibility of logic design Er is to implement architecture given by architect . For better design , design engineer puts much effort on bug free quality design, less number of logic gates which implements the design, so that it will have low power consumption. Most of design have clock disable feature ,
implication operator as it name suggest it is something related to “the conclusion that can be drawn from something” same thing is valid for system verilog as well where can you use in SV , it will be used where you want certain things you want to constraint certain things based on certain value/expression/signal consider
When the size of the collection is unknown or the data space is sparse, an associative array is used, which does not have any storage allocated until it is used. That means, it is dynamically allocated, but has non-contiguous elements. Associative array’s index expression is not restricted to integral expressions, but can be of any