How to randomize a class in system verilog ?

Write system verilog code to generate packet value between 10 to 100, if packet type is “Good”

// Code your testbench here
// or browse Examples

// Run randomized classs
//testbench4u.com
typedef enum {good, bad} packet1;

class txn_crc;
rand bit [7:0] crc;
rand bit [8:0] packet;
rand packet1 packet_type ;
constraint packet_width {
if (packet_type==good)
{
packet<=100;
packet>=10;
}
}

endclass

module test;
initial begin
txn_crc txn_type ;

repeat (10 ) begin
txn_type= new();
assert(txn_type.randomize());
$display(“value of pcaket = %d, =%s” ,txn_type.packet,txn_type.packet_type );

end

end

endmodule: test