always and initial block , how to use them ??

These are two block in verilog/system verilog which is used  for  writing Verilog behavioural code.

initial block : it executes only once in time zero

always block : As its name suggest , it  is  like infinity loop if there are no conditions are supplied, in case of some condition, it will execute on the given condition.

always @(<condition> <signal>)

<condition> <signal> are sensitivity list , so changes in sensitivity list will be seen by always block and it 
executes the hdl code inside it.

Where <condition> can be either posedge, negedge, or omitted. The <signal> is used to provide synchronisation in the
 the circuit.  
  
Note : Always and initial can't be used together 

Lets See Some Example

module useof_initial();
reg clock,reset,enable,data;

initial begin
 clock = 0;
 reset = 0;
 enable = 1;
 data = 1;
 $display( "At time=%0t Value of clk=%0b, reset=%0b,enable=%0b,data=%0b",$time,clock, reset,enable,data);

end endmodule : useof_initial

Output

At time=0 Value of clk=0, reset=0,enable=1,data=1

Values are printed at time zero , also it was executed only once.

module useof_always();
reg clk,reset,enable,q_in,data;

initial begin
reset=0;
clk =0;
#5;
clk= 1;
q_in=1;
enable=1;
end

always @ (posedge clk) begin
if (reset) begin
data = 0;
end else if (enable) begin
data = q_in;
end

$display(“At time =%0t, Value of reset=%0b,Data Value=%0b”,$time,reset ,data);
end

endmodule:useof_always

Output 

At time =5, Value of reset=0,Data Value=1

in above example posedge clk is put in sensitivity list and hence when clk is high in time 5 unit, hdl code are executed.

as it is blocking evaluation RHS and assignment were done at same time , hence values are seen accordingly