1. Why is there no wait signal on the APB?
The APB has been designed to implement as simple an interface as possible. Having this simple design makes it much easier to connect new APB peripherals and makes the analysis of the system performance easier to calculate. Although many APB peripherals are slow devices, such as UARTs, they are normally accessed via control registers. Typically the driver software will first access a status register to determine that data is available
and only then access the data register. Both of these accesses are possible without the addition of wait states and therefore the peripheral can easily be accessed as an APB device. Peripherals which do require wait states can be designed as AHB slaves and in the rare case that a design does include a large number of these peripherals then a secondary stub AHB can be used to reduce the loading on the main system bus.
2. How should AHB to APB bridges handle accesses that are not 32-bits?
The bridge should simply pass the entire 32-bit data bus through the bridge. Please note that when transfers less than 32-bits are performed to an APB slave it is important to ensure that the peripheral is located on the appropriate bits of the APB data bus