Verilog language supports two types of assignments: blocking and nonblocking. In blocking assignments, evaluation and assignment happens immediately. Thus, if there are multiple blocking assignments in a sequential block, each statement execution follows in a blocking way as shown below.
always @(posedge clk) begin
x = a|b;
y = a&b;
z = x|y;
end
In this example, each statement uses blocking assignments and the values of a and b are evaluated and assigned to x and y immediately as the statements execute in order. Hence, in third statement, the new values of x and y are evaluated and assigned to z. In nonblocking assignments, all assignments are deferred until end of current simulation tick. Hence, evaluation of entire RHS (Right Hand Side) happens first and only then assignment to LHS happens.
always @(posedge clk) begin
x <= a|b;
y <= a&b;
z <= x|y;
end
In this example, the RHS of each of the three statements are evaluated first and only after that the assignments to each of LHS (left hand side) happens. Hence, you can notice that in this case, the old values of x and y are OR’ed and assigned to z.
Blocking statement are executed in the Active region of Verilog Stratified Event Queue while Evaluation of RHS of Nonblocking statement occurred in Active Region and updation of LHS side happen in NBA region.