Can you pass config value in interface in System Verilog ?

Yes ,

Answer to this question is take help of assign keyword and assign the one module signal to another module signal based on condition passed through config files

Lets see how can you do it

assign x.y_signal= sknobs::get_string(“+a.b.c.d.e.config=rtl”,”rtl”) == “rtl” ? ‘h0 : a.b.c.d.signal_dest;