Hardware Design and Verification
Definition : Fifo (synchronous ) The Synchronous FIFO has a single clock port for both data-read and data-write operations, it means it is used for synchronising across two process when two process are running on same clock. One source writes to the FIFO and the other sources reads out the FIFO where it sees the order
Well, Lets take adder of following specification : it is one bit adder , one result , one bit carry So system verilog interface port definition will look like interface dut_if1; logic a_in, b_in, c_in; logic sum_out; logic carry_out; logic clock,reset; endinterface So Lets go through definition of each component , click here to get details information
Welcome to section uvm question and answer part , I will try to put around 20 to 30 questions and answer related to UVM Lets Start What is a virtual sequence and where do we use a virtual sequence? What are its benefits? company favorite question A virtual sequence is a sequence which controls stimulus
Welcome to section uvm question and answer part2 , I will try to put around 20 to 30 questions and answer related to UVM Lets Start What are the different arbitration mechanisms available for a Sequencer? Multiple sequences can interact concurrently with a driver connected to a single interface. The sequencer supports an arbitration mechanism
Welcome to section uvm question and answer part1 , I will try to put around 20 to 30 questions and answer related to UVM Lets Start What are some of the benefits of UVM methodology? UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology
