Welcome to section uvm question and answer part1 , I will try to put around 20 to 30 questions and answer related to UVM Lets Start What are some of the benefits of UVM methodology? UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology
What is difference between queue and mailbox? A mailbox is a built-in class around a queue that uses semaphores to control access to the ends of a queue. A mailbox only has FIFO element ordering whereas you can access the head, tail, or middle elements of a queue. you typically use a mailbox when there
How many parallel processes does this code generate? fork for (int i=0; i < 10; i++ ) begin ABC(); end join Since the “for” loop is inside the fork join, it executes as a single thread. Which keyword in SystemVerilog is used to define Abstract classes? Sometimes a class is defined with an intention to
What is extern ? extern qualifier indicates that the body of the method (its implementation) is to be found outside the class declaration. before the method name, class name should be specified with class resolution operator to specify to which class the method corresponds to. Example-1: In the example below, creating the object of virtual class
First One need to calculate no of block in cache, by dividing the total cache size by each cache line size and then no of sets is evaluated by dividing no of block by x (x is way set associative ) index bit : no of bit used to represent each cache line size remaining
What is the difference between new() and new[] in SystemVerilog? The function new() is the class constructor function in SystemVerilog. It is defined in a class to initialize data members of the class. The new[] operator is used to allocate memory for a dynamic array. The size of the dynamic array that needs to be
UVM config DB The configuration database provide access to a centralized database where type specific information can be stored and received. config_db can contain scalar objects, class handles, queues, lists, or even virtual interfaces. The database has both a name table and a type table and each resource is entered into both. Resources are stored
What is the difference between a reg, wire and logic in SystemVerilog? reg and wire are two data types that existed from Verilog, while logic is a new data type that was introduced in SystemVerilog. 1) A wire is a data type that can model physical wires to connect two elements. Wires can only be
Question asked write a constraint if address is within 100K it can have x1 and y1 state , if it goes beyond that it will have z1 state, if it x1 state it can have good and bad state otherwise it will idle state write a logic if class is instantiated n1 times , counter
what is difference between uvm_config_db and uvm_resource_db ? where we use task in uvm phases? difference between posedge and rise ? what is property in assertion ? what will be output of below code fork add(2,3); #10 add(3,3); join task add(int a, int b) int c = a +b; display(“a= %0d, b=%0d, c=%0d”, a,b,c); endtask
