How to randomize a class in system verilog ?
System Verilog 0 CommentsWrite system verilog code to generate packet value between 10 to 100, if packet type is “Good” // Code your testbench here // or browse Examples // Run randomized classs //testbench4u.com typedef enum {good, bad} packet1; class txn_crc; rand bit [7:0] crc; rand bit [8:0] packet; rand packet1 packet_type ; constraint packet_width { if (packet_type==good)