AMBA AHB – Arbitration Questions
1.When should a master assert and deassert the HLOCK signal for a locked transfer?
The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at the start of the address phase. The master should deassert the HLOCK signal when the address phase of the last transfer in the locked sequence has started.
2. Can an arbiter be designed to always allow bursts to complete?
A SPLIT, RETRY or ERROR response from a slave can always cause a burst to be early terminated. This is outwith the control of the Arbiter and so must be supported.Undefined length INCR bursts cannot have their end point predicted, so there is no efficient way that an Arbiter design can allow the burst to complete before granting another master. INCR bursts must be arbitrated on a cycle by cycle basis. Defined length INCRx and WRAPx bursts can have their beats counted, and so allowed to complete by the Arbiter. However because of the AHB arbitration synchronous timing, there is no way to avoid possibly terminating a burst immediately after the first transfer of the burst has been indicated. The Arbiter only knows that a defined length burst is in progress by sampling the HBURST bus. However the first point at which HBURST can be sampled is after the first clock cycle of the first burst beat, by which time the Arbiter may already have decided to grant another master and will have changed the HGRANT outputs accordingly. Only a combinatorial path from HBURST to HGRANT would allow the burst to be detected in time to avoid early termination in this scenario, but combinatorial paths in the AHB bus
are not allowed. ask ARM
3. Why is HADDR sometimes shown as an input to the arbiter?
The address bus, HADDR, is not required as an input to the arbiter but in some system designs it may be useful to use the address bus to determine a good point to change over between bus masters. For example, the arbiter could be designed to change bus ownership when a burst of transfers reaches a quad word boundary.
4. When can the HGRANT signal change?
The HGRANT signal can change in any cycle and the following cases are possible:
* It is possible that the HGRANT signal may be asserted and then removed before the current transfer
completes. This is acceptable because the HGRANT signal is only sampled by masters when HREADY is
high.
* A master can be granted the bus without requesting it.
* The above point also means that it is possible to be granted the bus in the same cycle that it is
requested. This can occur if the master is coincidentally granted the bus in the same cycle that it
requests it.
5. What is the relationship between the HLOCK signal and the HMASTLOCK signal?
At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the master that is about to start driving the address bus and if HLOCK is asserted at this point then HMASTLOCK will be asserted by the arbiter for the duration of the address phase of the transfer.
6. When should a master deassert its HBUSREQ signal?
For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has started the address phase of the last transfer in the burst. This will mean that if the penultimate transfer in the burst is zero wait state then the master may be granted the bus for an additional transfer at the end of an undefined length burst. For a defined length burst the master can deassert the HBUSREQ signal once the master has been
granted the bus for the first transfer. This can be done because the arbiter is able to count the transfers in the burst and keep the master granted until the burst completes. However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has been completed.
7. When will the arbiter grant another master after a locked transfer?
The arbiter will always grant the master an extra transfer at the end of a locked sequence, so the master is guaranteed to perform one transfer with the HMASTLOCK signal low at the end of the locked sequence. This coincides with the data phase of the last transfer in the locked sequence.
During this time the arbiter can change the HGRANT signals to a new bus master, but if the data phase of the last locked transfer receives either a SPLIT or RETRY response then the arbiter will drive the HGRANT signals to ensure that either the master performing the locked sequence remains granted on the bus for a RETRY response, or the Dummy master is granted the bus for the SPLIT response.
8. Can a master deassert HLOCK during a burst?
The AHB specification requires that all address phase timed control signals (other than HADDR and HTRANS) remain constant for the duration of a burst. Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK signal which is address phase timed.Therefore HLOCK must remain high for the duration of a burst, and can only be deasserted such that the following HMASTLOCK signal changes after the final address phase of the burst.
9. If a master is currently granted the bus by default, how many cycles before starting an non-IDLE
transfer does it have to assert HBUSREQ?
None. It can start a non IDLE transfer immediately.
10. Can a master perform transfers other than IDLE when the bus was granted to it, but not requested
by the master?
Yes. A master can perform transfers other than IDLE when it had not requested the bus. Please note that in this case it is still recommended that the master asserts its request signal so that the arbiter does not change ownership of the bus to a lower priority master while the transfers are in progress.