Hardware Design and Verification
Well, Lets take adder of following specification : it is one bit adder , one result , one bit carry So system verilog interface port definition will look like interface dut_if1; logic a_in, b_in, c_in; logic sum_out; logic carry_out; logic clock,reset; endinterface So Lets go through definition of each component , click here to get details information
Write system verilog code to generate packet value between 10 to 100, if packet type is “Good” // Code your testbench here // or browse Examples // Run randomized classs //testbench4u.com typedef enum {good, bad} packet1; class txn_crc; rand bit [7:0] crc; rand bit [8:0] packet; rand packet1 packet_type ; constraint packet_width { if (packet_type==good)
Virtual sequencer : it contains handles of the sequencer which are located in different agent Q. Question is when do we use it ?? Why do use it if something has to be synchronized , in general stimulus generation across different interface has to be synchronized, which is done by Virtual sequencer , virtual sequences
Q. Lets take a adder has port definition Input port ( A : 1, B : 1 bit , C: 1 bit ) Output port( Sum : 1 bit, carry : 1 bit ) Write UVM sequence item ? Answer : Lets define a_in ,
UVM resource Db : it is configuration data base , doesn’t have hierarchy like UVM config db so if one units some value to it , it can access by any where UVM config Db : it is configuration data base which inherit property from UVM resource DB also it has component hierarchy, higher in
VLSI: As its full name is “ Very large scale integration” , something to do with large no of transistors integration. Where VLSI is used : it is used to develop any electronic device with a lot of functionalities Like : Mobile processor , Computer processor /server , Bluetooth device /Wireless Device /Memory Now if
What is the difference between a reg, wire and logic in SystemVerilog? reg and wire are two data types that existed from Verilog, while logic is a new data type that was introduced in SystemVerilog. 1) A wire is a data type that can model physical wires to connect two elements. Wires can only be
Question asked write a constraint if address is within 100K it can have x1 and y1 state , if it goes beyond that it will have z1 state, if it x1 state it can have good and bad state otherwise it will idle state write a logic if class is instantiated n1 times , counter
what is difference between uvm_config_db and uvm_resource_db ? where we use task in uvm phases? difference between posedge and rise ? what is property in assertion ? what will be output of below code fork add(2,3); #10 add(3,3); join task add(int a, int b) int c = a +b; display(“a= %0d, b=%0d, c=%0d”, a,b,c); endtask
What are different types of assertions? What are the differences between Immediate and Concurrent assertions? What is the difference between simple immediate assertion and deferred immediate assertions? What is the difference between simple immediate assertion and deferred immediate assertions? What are the advantages of writing a checker using SVA (SystemVerilog Assertions) as compared to writing
